In the prior manufacturing technology of semiconductor devices, polymer is usually used to form a dielectric layer in a manufacturing process or a packaging process, and a copper wiring process is implemented on the polymer surface of the dielectric layer. However, the uniformity of the polymer surface is not good, which cannot meet the requirements of high density integration and advanced packaging.
For example, in the prior manufacturing process of an interposer, polymer (e.g. polyimide or BCB) is used to form a substrate. The uniformity of the polymer surface is around +/−10%, and the TTV (total thickness variation) of the 40 um-thickness substrate is around 4 um. A rough polymer surface is unfavorable for following processes including etching, PVD and electroplating. The prior common method to solve this problem is depositing a SiO2 dielectric layer on the substrate through a CVD process; however this method is costly and complicated. Even by spin coating the polymer surface of the substrate, the uniformity of the polymer surface is only roughly improved and still cannot meet the requirement of high density integration.
Damascene technology is widely applied in semiconductor manufacture to form copper wires. A common damascene process includes: forming a dielectric layer on a silicon substrate; etching via-holes on the dielectric layer; forming a barrier layer; and depositing copper in the via-holes. In a prior damascene process used in a TSV interposer process, before depositing copper in the via-holes, copper seed layer is further formed in the hole through a PVD process. Finally, the copper exposed outside the dielectric layer should be removed through a CMP process to form copper wires.
In the prior damascene process, the dielectric layer may be formed through a CVD process. Though the process is reliable and internal holes are easy to be controlled, the CVD process is highly cost. Polymer may also be used to form a dielectric layer. However, the uniformity of the polymer surface is not good, which is only favorable for a large-line-width integration and cannot meet the requirement of high density integration.
RDL technology is also widely applied in semiconductor manufacture. In a prior RDL process, to reduce the cost and simplify the process, the outer dielectric layer is made of polymer (e.g. polyimide or BCB). However, the rough surface of the polymer outer dielectric layer is unfavorable for a multi-layer RDL process and cannot meet the requirements of high density integration. The uniformity of the polymer surface may get worse and worse with the increase of RDL layers. Therefore, only 2˜3 layers RDL process could be achieved in the prior art, it is difficult to successfully implement a more than 3 layers RDL process.